Display device and method of driving the same

ABSTRACT

A display device may include a display panel including a gate line, a data line, and a pixel electrically connected to the gate line and the data line, where display panel displays an image based on input image data, a gate driver which outputs a gate signal to the gate line, a data driver which outputs a data voltage to the data line, and a power supply voltage generator which provides a driving voltage to the display panel, the gate driver and the data driver. The power supply voltage generator generates a gate clock signal based on an on-clock signal and an off-clock signal and changes a count value of the on-clock signal or the off-clock signal when the gate clock signal is an abnormal signal.

This application claims priority to Korean Patent Application No.10-2020-0185867, filed on Dec. 29, 2020, and all the benefits accruingtherefrom under 35 U.S.C. § 119, the content of which in its entirety isherein incorporated by reference.

BACKGROUND 1. Field

The disclosure relates to a display device and a method of driving thedisplay device, and more particularly, to a display device and a methodof driving the display device, in which an abnormal signal of a gateclock signal is corrected into a normal signal.

2. Description of the Related Art

In general, a display device may include a display panel and a displaypanel driver. The display panel may display an image based on inputimage data, and may include a plurality of gate lines, a plurality ofdata lines, and a plurality of pixels. The display panel driver mayinclude a gate driver configured to provide a gate signal to the gatelines, a data driver configured to provide a data voltage to the datalines, a driving controller configured to control the gate driver andthe data driver, and a power supply voltage generator configured toprovide a driving voltage to the display panel, the gate driver, and thedata driver.

SUMMARY

In a display device, an on-clock signal and an off-clock signal may beabnormally output due to a malfunction of the driving controller causedby an external factor such as static electricity or a momentaryelectrical surge. When the on-clock signal and the off-clock signal ofthe display device are abnormally output, an abnormal display screen maybe displayed on a display panel. Therefore, when the on-clock signal andthe off-clock signal are abnormally output, it is desired to correct agate clock signal.

Embodiments of the disclosure provide a display device capable ofdetecting an abnormal gate clock signal and correcting the gate clocksignal into a normal signal, thereby improving reliability.

Embodiments of the disclosure provide a method of driving a displaydevice, capable of detecting an abnormal gate clock signal andcorrecting the gate clock signal into a normal signal, thereby improvingreliability.

According to an embodiment of the invention, a display device includes adisplay panel including a gate line, a data line, and a pixelelectrically connected to the gate line and the data line, where thedisplay panel displays an image based on input image data, a gate driverwhich outputs a gate signal to the gate line, a data driver whichoutputs a data voltage to the data line, and a power supply voltagegenerator which provides a driving voltage to the display panel, thegate driver, and the data driver. In such an embodiment, the powersupply voltage generator generates a gate clock signal based on anon-clock signal and an off-clock signal and changes a count value of theon-clock signal or the off-clock signal when the gate clock signal is anabnormal signal.

In an embodiment, the power supply voltage generator may determinewhether the gate clock signal is the abnormal signal based on a lengthof an activation period of the gate clock signal.

In an embodiment, the power supply voltage generator may calculate agate clock reference time by calculating a time during which theactivation period of the gate clock signal is maintained based on theon-clock signal and the off-clock signal.

In an embodiment, the power supply voltage generator may obtain a gateclock actual time by feeding back the gate clock signal output from anoutput terminal of the power supply voltage generator and determine thegate clock signal as the abnormal signal when the gate clock referencetime and the gate clock actual time are different from each other.

In an embodiment, the power supply voltage generator may count anactivation period of the on-clock signal or the off-clock signal andgenerate the gate clock signal corresponding to the count value of theon-clock signal or the off-clock signal.

In an embodiment, the power supply voltage generator may adjust thelength of the activation period of the gate clock signal by increasingor decreasing the count value of the on-clock signal or the off-clocksignal when the gate clock signal is the abnormal signal.

In an embodiment, the power supply voltage generator may include acalculator which calculates a gate clock reference time by calculating atime during which the activation period of the gate clock signal ismaintained based on the on-clock signal and the off-clock signal, acomparator which obtains a gate clock actual time by feeding back thegate clock signal output from an output terminal and compares the gateclock reference time with the gate clock actual time, and a gatecontroller which outputs the gate clock signal to the output terminaland corrects the gate clock signal into a normal signal by increasing ordecreasing the count value of the on-clock signal or the off-clocksignal when the gate clock signal is the abnormal signal.

In an embodiment, the calculator may calculate the gate clock referencetime as a multiplication of a time during which an activation period ofthe on-clock signal is maintained and a number of types of the gateclock signal.

In an embodiment, the comparator may generate a clock recovery signalwhen the gate clock reference time and the gate clock actual time aredifferent from each other and transmit the clock recovery signal to thegate controller.

In an embodiment, the gate controller may recover a count value before aloss of the on-clock signal by decreasing the count value of theon-clock signal when the gate clock signal is the abnormal signal due tothe loss of the on-clock signal.

In an embodiment, the gate controller may recover a count value before aloss of the off-clock signal by increasing the count value of theoff-clock signal when the gate clock signal is the abnormal signal dueto the loss of the off-clock signal.

According to an embodiment of the invention, a method of driving adisplay device includes generating an on-clock signal and an off-clocksignal, generating a gate clock signal based on the on-clock signal andthe off-clock signal, determining whether the gate clock signal is anabnormal signal based on a length of an activation period of the gateclock signal, and changing a count value of the on-clock signal or theoff-clock signal when the gate clock signal is the abnormal signal.

In an embodiment, the method may further include calculating a gateclock reference time by calculating a time during which the activationperiod of the gate clock signal is maintained based on the on-clocksignal and the off-clock signal.

In an embodiment, a gate clock actual time may be obtained by feedingback the gate clock signal output from an output terminal, and the gateclock signal may be determined as the abnormal signal when the gateclock reference time and the gate clock actual time are different fromeach other.

In an embodiment, the method may further include counting an activationperiod of the on-clock signal or the off-clock signal and generating thegate clock signal corresponding to the count value of the on-clocksignal or the off-clock signal.

In an embodiment, the length of the activation period of the gate clocksignal may be adjusted by increasing or decreasing the count value ofthe on-clock signal or the off-clock signal when the gate clock signalis the abnormal signal.

In an embodiment, the method may further include calculating a gateclock reference time by calculating a time during which the activationperiod of the gate clock signal is maintained based on the on-clocksignal and the off-clock signal, obtaining a gate clock actual time byfeeding back the gate clock signal output from an output terminal, andcomparing the gate clock reference time with the gate clock actual time.In such an embodiment, the gate clock signal may be output to the outputterminal, and the gate clock signal may be corrected into a normalsignal by increasing or decreasing the count value of the on-clocksignal or the off-clock signal when the gate clock signal is theabnormal signal.

In an embodiment, the calculating the gate clock reference time mayinclude calculating the gate clock reference time as a multiplication ofa time during which an activation period of the on-clock signal ismaintained and a number of types of the gate clock signal.

In an embodiment, the comparing the gate clock reference time with thegate clock actual time may include generating a clock recovery signalwhen the gate clock reference time and the gate clock actual time aredifferent from each other.

In an embodiment, the on-clock signal may be recovered to have a countvalue before a loss of the on-clock signal by decreasing the count valueof the on-clock signal when the gate clock signal is the abnormal signaldue to the loss of the on-clock signal, and the off-clock signal may berecovered to have a count value before a loss of the off-clock signal byincreasing the count value of the off-clock signal when the gate clocksignal is the abnormal signal due to the loss of the off-clock signal.

According to embodiments of the display device and the method of drivingthe display device as described above, the display device may detect anabnormal gate clock signal caused by the loss of the on-clock signal orthe off-clock signal and may correct the gate clock signal into a normalsignal. Accordingly, in such embodiments of the display device, visualrecognition of noise by a user may be minimized, and display qualitydefects of the display device may be reduced. As a result, in suchembodiments of the display device, safety and reliability of the displaydevice may be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a display device according to anembodiments

FIG. 2 is a plan view showing an embodiment of the display device ofFIG. 1.

FIG. 3 is a timing diagram showing an embodiment of input and outputsignals of a power supply voltage generator in FIG. 1.

FIG. 4 is a block diagram showing an embodiment of a power supplyvoltage generator in FIG. 1.

FIG. 5 is a timing diagram showing a case in which a gate clock signalis an abnormal signal.

FIG. 6 is a diagram showing a display panel in which noise is generatedby the abnormal signal of FIG. 5.

FIG. 7 is a timing diagram showing a gate clock signal corrected into anormal signal when a gate clock signal is an abnormal signal in anembodiment.

FIG. 8 is a diagram showing a display panel in which a noise iscorrected by the gate clock signal correction of FIG. 7.

FIG. 9 is a flowchart showing an operation of a display device accordingto an embodiment.

FIG. 10 is a flowchart showing an operation of a display deviceaccording to an alternative embodiment.

FIG. 11 is a timing diagram showing an alternative embodiment of inputand output signals of the power supply voltage generator 600 in FIG. 1.

DETAILED DESCRIPTION

The invention now will be described more fully hereinafter withreference to the accompanying drawings, in which various embodiments areshown. This invention may, however, be embodied in many different forms,and should not be construed as limited to the embodiments set forthherein. Rather, these embodiments are provided so that this disclosurewill be thorough and complete, and will fully convey the scope of theinvention to those skilled in the art. Like reference numerals refer tolike elements throughout.

It will be understood that when an element is referred to as being “on”another element, it can be directly on the other element or interveningelements may be present therebetween. In contrast, when an element isreferred to as being “directly on” another element, there are nointervening elements present.

It will be understood that, although the terms “first,” “second,”“third” etc. may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another element, component, region, layer orsection. Thus, “a first element,” “component,” “region,” “layer” or“section” discussed below could be termed a second element, component,region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. As used herein,“a”, “an,” “the,” and “at least one” do not denote a limitation ofquantity, and are intended to include both the singular and plural,unless the context clearly indicates otherwise. For example, “anelement” has the same meaning as “at least one element,” unless thecontext clearly indicates otherwise. “At least one” is not to beconstrued as limiting “a” or “an.” “Or” means “and/or.” As used herein,the term “and/or” includes any and all combinations of one or more ofthe associated listed items. It will be further understood that theterms “comprises” and/or “comprising,” or “includes” and/or “including”when used in this specification, specify the presence of statedfeatures, regions, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, regions, integers, steps, operations, elements,components, and/or groups thereof

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The term “lower,” cantherefore, encompasses both an orientation of “lower” and “upper,”depending on the particular orientation of the figure. Similarly, if thedevice in one of the figures is turned over, elements described as“below” or “beneath” other elements would then be oriented “above” theother elements. The terms “below” or “beneath” can, therefore, encompassboth an orientation of above and below.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent disclosure, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Embodiments described herein should not be construed as limited to theparticular shapes of regions as illustrated herein but are to includedeviations in shapes that result, for example, from manufacturing. Forexample, a region illustrated or described as flat may, typically, haverough and/or nonlinear features. Moreover, sharp angles that areillustrated may be rounded. Thus, the regions illustrated in the figuresare schematic in nature and their shapes are not intended to illustratethe precise shape of a region and are not intended to limit the scope ofthe present claims.

Hereinafter, embodiments of the disclosure will be described in detailwith reference to the accompanying drawings.

FIG. 1 is a block diagram showing a display device 10 according to anembodiment.

Referring to FIG. 1, an embodiment of a display device 10 may include adisplay panel 100 and a display panel driver. The display panel drivermay include a driving controller 200, a gate driver 300, a gammareference voltage generator 400, and a data driver 500. The displaypanel driver may further include a power supply voltage generator 600.

In one embodiment, for example, the driving controller 200 and the datadriver 500 may be integrally formed. In one embodiment, for example, thedriving controller 200, the gamma reference voltage generator 400, andthe data driver 500 may be integrally formed as a single unit, e.g., asingle circuit unit. A driving module in which at least the drivingcontroller 200 and the data driver 500 are integrally formed may bereferred to as a timing controller-embedded data driver (“TED”).

The display panel 100 may include a display part for displaying an imageand a peripheral part adjacent to the display part.

The display panel 100 may include a plurality of gate lines GL, aplurality of data lines DL, and a plurality of pixels P electricallyconnected to the gate lines GL and the data lines DL, respectively. Thegate lines GL may extend in a first direction D1, and the data lines DLmay extend in a second direction D2 intersecting the first direction D1.

The driving controller 200 may receive input image data IMG and an inputcontrol signal CONT from an external device (not shown). In oneembodiment, for example, the input image data IMG may include red imagedata, green image data, and blue image data. The input image data IMGmay further include white image data. Alternatively, the input imagedata IMG may include magenta image data, yellow image data, and cyanimage data. The input control signal CONT may include a master clocksignal and a data enable signal. The input control signal CONT mayfurther include a vertical synchronization signal and a horizontalsynchronization signal.

The driving controller 200 may generate a first control signal CONT1, asecond control signal CONT2, a third control signal CONT3, and a datasignal DATA based on the input image data IMG and the input controlsignal CONT.

The driving controller 200 may generate the first control signal CONT1for controlling an operation of the gate driver 300 based on the inputcontrol signal CONT to output the generated first control signal CONT1to the gate driver 300. The first control signal CONT1 may include avertical start signal.

The driving controller 200 may generate the second control signal CONT2for controlling an operation of the data driver 500 based on the inputcontrol signal CONT to output the generated second control signal CONT2to the data driver 500. The second control signal CONT2 may include ahorizontal start signal and a load signal.

The driving controller 200 may generate the data signal DATA based onthe input image data IMG. The driving controller 200 may output the datasignal DATA to the data driver 500.

The driving controller 200 may generates the third control signal CONT3for controlling an operation of the gamma reference voltage generator400 based on the input control signal CONT to output the generated thirdcontrol signal CONT3 to the gamma reference voltage generator 400.

The gate driver 300 may generate gate signals for driving the gate linesGL in response to the first control signal CONT1 received from thedriving controller 200. The gate driver 300 may output the gate signalsto the gate lines GL. In one embodiment, for example, the gate driver300 may sequentially output the gate signals to the gate lines GL. In anembodiment, the gate driver 300 may be implemented as an amorphoussilicon gate (“ASG”) circuit using an amorphous silicon thin filmtransistor (“a-Si TFT”), and may be mounted on the peripheral part ofthe display panel 100. According to an alternative embodiment, the gatedriver 300 may be implemented by using an oxide semiconductor, acrystalline semiconductor, a polycrystalline semiconductor, or the like,and may be mounted on the peripheral part of the display panel 100.

The gamma reference voltage generator 400 may generate a gamma referencevoltage VGREF in response to the third control signal CONT3 receivedfrom the driving controller 200. The gamma reference voltage generator400 may provide the gamma reference voltage VGREF to the data driver500. The gamma reference voltage VGREF may have a value corresponding toeach data signal DATA.

In an embodiment of the disclosure, the gamma reference voltagegenerator 400 may be disposed in the driving controller 200 or in thedata driver 500.

The data driver 500 may receive the second control signal CONT2 and thedata signal DATA from the driving controller 200, and may receive thegamma reference voltage VGREF from the gamma reference voltage generator400. The data driver 500 may convert the data signal DATA into an analogdata voltage by using the gamma reference voltage VGREF. The data driver500 may output the data voltage to the data line DL. In one embodiment,for example, the data driver 500 may be mounted on the peripheral partof the display panel 100. In one embodiment, for example, the datadriver 500 may be integrated in the peripheral part of the display panel100.

The power supply voltage generator 600 may provide a power supplyvoltage to at least one selected from the display panel 100, the drivingcontroller 200, the gate driver 300, the gamma reference voltagegenerator 400 and the data driver 500. In an embodiment, the powersupply voltage generator 600 may include a direct current-to-directcurrent (“DC-DC”) converter. The power supply voltage generator 600 maygenerate a common voltage VCOM based on an input voltage VIN to outputthe generated common voltage VCOM to the display panel 100. According toan embodiment, the display device 10 may be a liquid crystal displaydevice 10 including a liquid crystal layer. However, the disclosure isnot limited to the liquid crystal display 10.

In an embodiment, the power supply voltage generator 600 may generate agate clock signal CKV and a gate start signal STVP, which are used togenerate the gate signal, to output the generated gate clock signal CKVand the generated gate start signal STVP to the gate driver 300. Thepower supply voltage generator 600 may receive an on-clock signal ONCLK, an off-clock signal OFF CLK, and a vertical start signal STV fromthe driving controller 200. The vertical start signal STV may be asignal representing or indicating the start of one frame. The powersupply voltage generator 600 may generate the gate clock signal CKV andthe gate start signal STVP based on the on-clock signal ON CLK, theoff-clock signal OFF CLK and the vertical start signal STV. In such anembodiment, the on-clock signal ON CLK may be synchronized with a risingedge of the gate clock signal, and the off-clock signal OFF CLK may besynchronized with a falling edge of the gate clock signal. In anembodiment, the power supply voltage generator 600 may generate ananalog high voltage AVDD for determining a level of the data voltage tooutput the generated analog high voltage AVDD to the data driver 500.

FIG. 2 is a plan view showing an embodiment of the display device 10 ofFIG. 1.

Referring to FIGS. 1 and 2, in an embodiment, the driving controller 200and the power supply voltage generator 600 may be disposed in a printedcircuit board assembly PBA. The printed circuit board assembly PBA maybe connected to a first printed circuit P1 and a second printed circuitP2.

In one embodiment, for example, the data driver 500 may include aplurality of data driver chips DIC connected between the first printedcircuit P1 and the display panel 100, and a plurality of data driverchips DIC connected between the second printed circuit P2 and thedisplay panel 100.

According to an embodiment, the gate driver 300 may be disposed in thedisplay panel 100. The power supply voltage generator 600 may outputgate clock signals CKV1 and CKV2 to the gate driver 300 disposed in thedisplay panel 100. The gate lines for applying the gate clock signalsCKV1 and CKV2 may be disposed on the display panel 100.

FIG. 3 is a timing diagram showing an embodiment of input and outputsignals of a power supply voltage generator 600 in FIG. 1.

Referring to FIGS. 1 to 3, the power supply voltage generator 600 mayreceive the on-clock signal ON CLK, the off-clock signal OFF CLK, andthe vertical start signal STV from the driving controller 200. The powersupply voltage generator 600 may generate the gate clock signal CKV andthe gate start signal STVP based on the on-clock signal ON CLK, theoff-clock signal OFF CLK, and the vertical start signal STV. In anembodiment, a rising time of each of gate clock signals at which thegate clock signal rises from a gate low voltage to a gate high voltagemay be determined by a rising edge of the on-clock signal ON CLK. Insuch an embodiment, a falling time of each of the gate clock signals atwhich the gate clock signal falls from the gate high voltage to the gatelow voltage may be determined by a falling edge of the off-clock signalOFF CLK. Each of a plurality of gate clock signals may have anactivation period (e.g., a gate high voltage period) that partiallyoverlaps an activation period of an adjacent gate clock signal. Thepower supply voltage generator 600 may generate the gate clock signalCKV and the gate start signal STVP to output the generated gate clocksignal CKV and the generated gate start signal STVP to the gate driver300. Although the gate clock signal has been illustrated in FIG. 3 asincluding two phases (e.g., 1 and 2 in the on-clock signal ON CLK andthe off-clock signal OFF CLK) and four clocks (e.g., first to fourthclock signals CKV1, CKV2, CKV3 (or CKV1B) and CKV4 (or CKV2B)),embodiments of the disclosure are not limited thereto, and a number oftypes of the gate clock signal may be further expanded.

In an embodiment, the on-clock signal ON CLK and the off-clock signalOFF CLK may be abnormally output due to a malfunction of the drivingcontroller 200 caused by an external factor such as static electricityor a momentary electrical surge. In this case, the gate clock signalgenerated by the power supply voltage generator 600 may also be anabnormal signal. If such an abnormal gate clock signal is input to thegate driver, the display panel may display an abnormal image. In anembodiment of the display device according to the invention, the powersupply voltage generator 600 may determine whether the gate clock signalis an abnormal signal, and change a count value of the on-clock signalON CLK or the off-clock signal OFF CLK when the gate clock signal is theabnormal signal such that the display panel may be effectively preventedfrom displaying the abnormal image. In an embodiment, the power supplyvoltage generator 600 may determine whether the gate clock signal is theabnormal signal based on a length of the activation period of the gateclock signal. When the gate clock signal is determined as the abnormalsignal, the count value of the on-clock signal ON CLK or the off-clocksignal OFF CLK is changed, such that the gate clock signal may becorrected into a normal signal. When the gate clock signal is correctedinto the normal signal, the display panel may display a normal image.Accordingly, in such an embodiment of the display device, visualrecognition of noise by a user may be minimized, and display qualitydefects of the display device may be reduced. An embodiment of a methodof correcting the gate clock signal will be described in detail belowwith reference to FIGS. 4 to 8.

FIG. 4 is a block diagram showing an embodiment of a power supplyvoltage generator 600 in FIG. 1.

Referring to FIG. 4, an embodiment of the power supply voltage generator600 may include a calculator 610, a comparator 620, and a gatecontroller 630. The calculator 610 may receive the on-clock signal ONCLK and the off-clock signal OFF CLK, and calculate a gate clockreference time CT. The comparator 620 may receive the gate clockreference time CT and a gate clock actual time RT, and generate a clockrecovery signal RS. The gate controller 630 may receive the on-clocksignal ON CLK and the off-clock signal OFF CLK, and generate the gateclock signal based on the clock recovery signal RS.

The calculator 610 may receive the on-clock signal ON CLK and theoff-clock signal OFF CLK, and calculate the gate clock reference timeCT. In an embodiment, the calculator 610 may receive the on-clock signalON CLK and the off-clock signal OFF CLK from the driving controller 200.The calculator 610 may calculate a time during which the activationperiod of the gate clock signal is maintained based on the on-clocksignal ON CLK and the off-clock signal OFF CLK. The calculator 610 maycalculate the gate clock reference time CT by calculating the timeduring which the activation period of the gate clock signal ismaintained. In an embodiment, the gate clock reference time CT may becalculated as a multiplication of a time during which an activationperiod of the on-clock signal ON CLK is maintained and the number oftypes of gate clock signals. The number of types of gate clock signalsmay be represented by phases and clocks of the gate clock signal. In oneembodiment, for example, when a time during which the activation periodof the on-clock signal ON CLK is maintained is one horizontal period(1H), and the number of types of gate clock signals is 2, the gate clockreference time CT may be 1H×2 phases. The gate clock reference time CTmay represent a time during which the activation period of the gateclock signal is set to be maintained when the gate clock signal is thenormal signal. The calculator 610 may transmit the gate clock referencetime CT to the comparator 620.

The comparator 620 may receive the gate clock reference time CT and thegate clock actual time RT, and generate the clock recovery signal RS. Inan embodiment, the comparator 620 may receive the gate clock referencetime CT from the calculator 610. The comparator 620 may obtain the gateclock actual time RT by feeding back the gate clock signal output froman output terminal OP of the power supply voltage generator 600. Thecomparator 620 may determine whether the gate clock reference time CTand the gate clock actual time RT are different from each other bycomparing the gate clock reference time CT with the gate clock actualtime RT. When the gate clock reference time CT and the gate clock actualtime RT are the same as each other, the gate clock signal may be thenormal signal. When the gate clock reference time CT and the gate clockactual time RT are different from each other, the gate clock signal maybe the abnormal signal. If the abnormal gate clock signal is input tothe gate driver, the display panel may display an abnormal image. Thecomparator 620 may generate the clock recovery signal RS when the gateclock reference time CT and the gate clock actual time RT are differentfrom each other. The comparator 620 may transmit the clock recoverysignal RS to the gate controller 630. The clock recovery signal RS mayallow the gate controller 630 to change a count value of an abnormalon-clock signal ON CLK or a count value of an abnormal off-clock signalOFF CLK.

The gate controller 630 may receive the on-clock signal ON CLK and theoff-clock signal OFF CLK, and generate the gate clock signal based onthe clock recovery signal RS. In an embodiment, the gate controller 630may receive the on-clock signal ON CLK and the off-clock signal OFF CLKfrom the driving controller 200. The gate controller 630 may generatethe gate clock signal based on the on-clock signal ON CLK and theoff-clock signal OFF CLK. The gate controller 630 may output the gateclock signal to the output terminal OP of the power supply voltagegenerator 600. The gate controller 630 may feedback and input the gateclock signal to the comparator 620. When the gate clock signal is theabnormal signal, the gate controller 630 may receive the clock recoverysignal RS from the comparator 620. The gate controller 630 may correctthe gate clock signal into a normal signal by increasing or decreasingthe count value of the on-clock signal ON CLK or the off-clock signalOFF CLK based on the clock recovery signal RS. In one embodiment, forexample, the gate controller 630 may receive the clock recovery signalRS, and adjust the length of the activation period of the gate clocksignal by increasing or decreasing the count value of the on-clocksignal ON CLK or the off-clock signal OFF CLK. In such an embodiment,the length of the activation period of the gate clock signal is adjustedin a way such that the gate clock signal may be corrected into thenormal signal. In such an embodiment, the gate clock signal is correctedinto the normal signal, such that the display panel may display a normalimage. Accordingly, in an embodiment of the display device, the visualrecognition of the noise by the user may be minimized, and the displayquality defects of the display device may be reduced.

FIG. 5 is a timing diagram showing a case in which a gate clock signalis an abnormal signal, FIG. 6 is a diagram showing a display panel inwhich noise is generated by the abnormal signal of FIG. 5, FIG. 7 is atiming diagram showing a gate clock signal corrected into a normalsignal when a gate clock signal is an abnormal signal in embodiments,and FIG. 8 is a diagram showing a display panel in which a noise iscorrected by the gate clock signal correction of FIG. 7.

Referring to FIGS. 3 to 6, in an embodiment, the power supply voltagegenerator 600 may receive the on-clock signal ON CLK, the off-clocksignal OFF CLK, and the vertical start signal STV from the drivingcontroller 200. The power supply voltage generator 600 may generate thegate clock signal CKV and the gate start signal STVP based on theon-clock signal ON CLK, the off-clock signal OFF CLK, and the verticalstart signal STV. The gate clock signal may be controlled based on theon-clock signal ON CLK and the off-clock signal OFF CLK. In oneembodiment, for example, a rising time of each of gate clock signals atwhich the gate clock signal rises from a gate low voltage to a gate highvoltage may be determined by a rising edge of the on-clock signal ONCLK. In one embodiment, for example, a falling time of each of the gateclock signals at which the gate clock signal falls from the gate highvoltage to the gate low voltage may be determined by a falling edge ofthe off-clock signal OFF CLK. Each of a plurality of gate clock signalsmay have an activation period (e.g., a gate high voltage period) thatpartially overlaps an activation period of an adjacent gate clocksignal. The power supply voltage generator 600 may generate the gateclock signal CKV and the gate start signal STVP to output the generatedgate clock signal CKV and the generated gate start signal STVP to thegate driver 300. Although FIG. 5 shows an embodiment where the gateclock signals have two phases and four clocks, embodiments of thedisclosure are not limited thereto.

In an embodiment, the power supply voltage generator 600 may count theactivation period of the on-clock signal ON CLK or the off-clock signalOFF CLK. In one embodiment, for example, the power supply voltagegenerator 600 may further include a counter configured to count theactivation period of the on-clock signal ON CLK or the off-clock signalOFF CLK. The counter may be disposed inside the power supply voltagegenerator 600, or may be disposed outside the power supply voltagegenerator 600 to communicate with the power supply voltage generator600. In an embodiment, as shown in FIG. 3, when the gate clock signalincludes two phases and four clocks, the counter may perform anoperation of dividing the activation period of the on-clock signal ONCLK or the off-clock signal OFF CLK into 1, 2, 3, and 4, and repeatedlycounting the divided activation period. The gate clock signal may becontrolled in synchronization with the count values of the on-clocksignal ON CLK and the off-clock signal OFF CLK. In one embodiment, forexample, the gate clock signal may be synchronized with a correspondingcount value of the on-clock signal ON CLK to rise from the gate lowvoltage to the gate high voltage. In one embodiment, for example, thegate clock signal may be synchronized with a corresponding count valueof the off-clock signal OFF CLK to fall from the gate high voltage tothe gate low voltage.

In an embodiment, the on-clock signal ON CLK and the off-clock signalOFF CLK may be lost by the malfunction of the driving controller 200caused by the external factor such as static electricity or a momentaryelectrical surge. In this case, the gate clock signal generated by thepower supply voltage generator 600 may be the abnormal signal (e.g.,“ERROR” in CKV1, CKV2, CKV3 and CVK4). When the abnormal gate clocksignal is input to the gate driver, the display panel may display anabnormal image. A part of the off-clock signal OFF CLK input to thepower supply voltage generator 600 may be lost. In this case, the gateclock signal may rise to the gate high voltage by the rising edge of theon-clock signal ON CLK, whereas the gate clock signal may not normallyfall to the gate low voltage due to the lost off-clock signal OFF CLK(“1st OFF CLK LOSS”). Therefore, the activation period of the gate clocksignal may be lengthened. As shown in FIG. 5, when a first off-clocksignal OFF CLK is lost, a first gate clock signal CKV1 may rise to thegate high voltage by a first on-clock signal ON CLK, whereas the firstgate clock signal CKV1 may fall to the gate low voltage by a secondoff-clock signal OFF CLK instead of the first off-clock signal.Similarly, a second gate clock signal CKV2 may rise to the gate highvoltage by a second on-clock signal ON CLK, whereas the second gateclock signal CKV2 may fall to the gate low voltage by a third off-clocksignal OFF CLK instead of the second off-clock signal OFF CLK. If such aphenomenon occurs, an overlapping period may be generated among the gateclock signals due to the abnormal gate clock signals. As shown in FIG.6, an image displayed on the display panel may have noise in a unit ofblock over the whole display panel because data corresponding to each ofthe gate clock signals is duplicated and output due to the overlappingof gate clock signals. Such noise in the unit of block may cause thedisplay quality defects, and may be visually recognized by the user.

In an embodiment of the display device according to the invention, thepower supply voltage generator 600 may determine whether the gate clocksignal is an abnormal signal, and change the count value of the on-clocksignal ON CLK or the off-clock signal OFF CLK when the gate clock signalis the abnormal signal. The power supply voltage generator 600 maydetermine whether the gate clock signal is the abnormal signal based onthe length of the activation period of the gate clock signal. When thegate clock signal is determined as the abnormal signal, the count valueof the on-clock signal ON CLK or the off-clock signal OFF CLK ischanged, such that the gate clock signal may be corrected into a normalsignal.

In an embodiment, as shown in FIGS. 7 and 8, when the on-clock signal ONCLK or the off-clock signal OFF CLK is lost, the comparator 620 maydetect the abnormal signal of the gate clock signal, and generate theclock recovery signal RS. The comparator 620 may transmit the clockrecovery signal RS to the gate controller 630. The gate controller 630may receive the clock recovery signal RS, and recover a counter value ofthe lost on-clock signal ON CLK or the lost off-clock signal OFF CLK. Insuch an embodiment, the gate controller 630 may recover a count valuebefore a loss of the on-clock signal ON CLK by decreasing the countvalue of the on-clock signal ON CLK when the gate clock signal is theabnormal signal due to the loss of the on-clock signal ON CLK. In suchan embodiment, the gate controller 630 may recover a count value beforea loss of the off-clock signal OFF CLK by increasing the count value ofthe off-clock signal OFF CLK when the gate clock signal is the abnormalsignal due to the loss of the off-clock signal OFF CLK. In oneembodiment, for example, when a first off-clock signal OFF CLK is lost,the gate controller 630 may increase a count value of a second off-clocksignal OFF CLK from 1 to 2 based on the clock recovery signal RS. Insuch an embodiment, the gate controller 630 may increase a count valueof a third off-clock signal OFF CLK from 2 to 3. In this case, a firstgate clock signal may be abnormally output, whereas a second gate clocksignal, a third gate clock signal, and a fourth gate clock signal may besynchronized with a normal off-clock signal OFF CLK to be output asnormal signals. In an embodiment, as shown in FIG. 8, the imagedisplayed on the display panel may be a normal image except for datacorresponding to the first gate clock signal, which is an abnormalsignal. In such an embodiment, noise in a unit of line may be generatedin the display panel. Such noise in the unit of line may not begenerally recognized by the user, so that the display quality defectsmay be minimized.

FIG. 9 is a flowchart showing an operation of a display device accordingto an embodiment.

Referring to FIGS. 1 and 4 to 9, an embodiment of a display device maygenerate an on-clock signal ON CLK and an off-clock signal OFF CLK(S110), generate a gate clock signal based on the on-clock signal ON CLKand the off-clock signal OFF CLK (S120), determine whether the gateclock signal is an abnormal signal based on a length of an activationperiod of the gate clock signal (S130), and change a count value of theon-clock signal ON CLK or the off-clock signal OFF CLK when the gateclock signal is the abnormal signal (S140).

In an embodiment, the display device may generate the on-clock signal ONCLK and the off-clock signal OFF CLK (S110), and generate the gate clocksignal based on the on-clock signal ON CLK and the off-clock signal OFFCLK (S120). In such an embodiment, a power supply voltage generator 600may receive the on-clock signal ON CLK, the off-clock signal OFF CLK,and a vertical start signal STV from a driving controller 200. The powersupply voltage generator 600 may generate the gate clock signal CKV anda gate start signal STVP based on the on-clock signal ON CLK, theoff-clock signal OFF CLK, and the vertical start signal STV. The gateclock signal may be controlled based on the on-clock signal ON CLK andthe off-clock signal OFF CLK. In one embodiment, for example, a risingtime of each of gate clock signals at which the gate clock signal risesfrom a gate low voltage to a gate high voltage may be determined by arising edge of the on-clock signal ON CLK. In one embodiment, forexample, a falling time of each of the gate clock signals at which thegate clock signal falls from the gate high voltage to the gate lowvoltage may be determined by a falling edge of the off-clock signal OFFCLK.

In an embodiment, the display device may determine whether the gateclock signal is an abnormal signal based on a length of an activationperiod of the gate clock signal (S130). In an embodiment, the calculator610 may calculate a time during which an activation period of the gateclock signal is maintained based on the on-clock signal ON CLK and theoff-clock signal OFF CLK. The calculator 610 may calculate a gate clockreference time CT by calculating the time during which the activationperiod of the gate clock signal is maintained. In such an embodiment,the gate clock reference time CT may be calculated as a multiplicationof a time during which an activation period of the on-clock signal ONCLK is maintained and a number of types of gate clock signals. Thecalculator 610 may transmit the gate clock reference time CT to thecomparator 620. The comparator 620 may obtain a gate clock actual timeRT by feeding back the gate clock signal output from an output terminalOP of the power supply voltage generator 600. The comparator 620 maydetermine whether the gate clock reference time CT and the gate clockactual time RT are different from each other by comparing the gate clockreference time CT with the gate clock actual time RT. When the gateclock reference time CT and the gate clock actual time RT are the same,the gate clock signal may be a normal signal. When the gate clockreference time CT and the gate clock actual time RT are different fromeach other, the gate clock signal may be the abnormal signal. Thecomparator 620 may generate a clock recovery signal RS when the gateclock reference time CT and the gate clock actual time RT are differentfrom each other, and transmit the clock recovery signal RS to the gatecontroller 630.

In an embodiment, the display device may change a count value of theon-clock signal ON CLK or the off-clock signal OFF CLK when the gateclock signal is the abnormal signal (S140). In detail, the gatecontroller 630 may receive the clock recovery signal RS, and recover acounter value of a lost on-clock signal ON CLK or a lost off-clocksignal OFF CLK. The gate controller 630 may recover a count value beforea loss of the on-clock signal ON CLK by decreasing the count value ofthe on-clock signal ON CLK when the gate clock signal is the abnormalsignal due to the loss of the on-clock signal ON CLK In an embodiment,the gate controller 630 may recover a count value before a loss of theoff-clock signal OFF CLK by increasing the count value of the off-clocksignal OFF CLK when the gate clock signal is the abnormal signal due tothe loss of the off-clock signal OFF CLK. In such an embodiment, a gateclock signal in which the on-clock signal ON CLK or the off-clock signalOFF CLK is lost may be abnormally output, whereas the remaining gateclock signals may be synchronized with a normal on-clock signal ON CLKor a normal off-clock signal OFF CLK so as to be output as normalsignals.

FIG. 10 is a flowchart showing an operation of a display deviceaccording to an alternative embodiment.

Referring to FIGS. 1 to 10, an alternative embodiment of a displaydevice may generate an on-clock signal ON CLK and an off-clock signalOFF CLK (S210), generate a gate clock signal based on the on-clocksignal ON CLK and the off-clock signal OFF CLK (S220), calculate a gateclock reference time CT by calculating a time during which an activationperiod of the gate clock signal is maintained based on the on-clocksignal ON CLK and the off-clock signal OFF CLK (S230), obtain a gateclock actual time RT by feeding back the gate clock signal output froman output terminal OP (S240), compare the gate clock reference time CTwith the gate clock actual time RT (S250), and correct the gate clocksignal into a normal signal by increasing or decreasing a count value ofthe on-clock signal ON CLK or the off-clock signal OFF CLK when the gateclock reference time CT and the gate clock actual time RT are differentfrom each other (S260).

In an embodiment, the display device may generate the on-clock signal ONCLK and the off-clock signal OFF CLK (S210), and generate the gate clocksignal based on the on-clock signal ON CLK and the off-clock signal OFFCLK (S220). In such an embodiment, a power supply voltage generator 600may receive the on-clock signal ON CLK, the off-clock signal OFF CLK,and a vertical start signal STV from a driving controller 200. The powersupply voltage generator 600 may generate the gate clock signal CKV anda gate start signal STVP based on the on-clock signal ON CLK, theoff-clock signal OFF CLK, and the vertical start signal STV. The gateclock signal may be controlled based on the on-clock signal ON CLK andthe off-clock signal OFF CLK. In one embodiment, for example, a risingtime of each of gate clock signals at which the gate clock signal risesfrom a gate low voltage to a gate high voltage may be determined by arising edge of the on-clock signal ON CLK. In one embodiment, forexample, a falling time of each of the gate clock signals at which thegate clock signal falls from the gate high voltage to the gate lowvoltage may be determined by a falling edge of the off-clock signal OFFCLK.

In an embodiment, the display device may calculate the gate clockreference time CT by calculating the time during which the activationperiod of the gate clock signal is maintained based on the on-clocksignal ON CLK and the off-clock signal OFF CLK (S230). In an embodiment,a calculator 610 may receive the on-clock signal ON CLK and theoff-clock signal OFF CLK from the driving controller 200. The calculator610 may calculate the time during which the activation period of thegate clock signal is maintained based on the on-clock signal ON CLK andthe off-clock signal OFF CLK. The calculator 610 may calculate the gateclock reference time CT by calculating the time during which theactivation period of the gate clock signal is maintained. In such anembodiment, the gate clock reference time CT may be calculated as amultiplication of a time during which an activation period of theon-clock signal ON CLK is maintained and a number of types of gate clocksignals. The number of types of gate clock signals may be represented byphases and clocks of the gate clock signal. In one embodiment, forexample, where a time during which the activation period of the on-clocksignal ON CLK is maintained is 1H, and the number of types of gate clocksignals is 2, the gate clock reference time CT may be 1H×2 phases. Thegate clock reference time CT may represent a time during which theactivation period of the gate clock signal is set to be maintained whenthe gate clock signal is the normal signal. The calculator 610 maytransmit the gate clock reference time CT to a comparator 620.

In an embodiment, the display device may obtain the gate clock actualtime RT by feeding back the gate clock signal output from the outputterminal OP (S240), and compare the gate clock reference time CT withthe gate clock actual time RT (S250). In such an embodiment, thecomparator 620 may receive the gate clock reference time CT from thecalculator 610. The comparator 620 may obtain the gate clock actual timeRT by feeding back the gate clock signal output from the output terminalOP of the power supply voltage generator 600. The comparator 620 maydetermine whether the gate clock reference time CT and the gate clockactual time RT are different from each other by comparing the gate clockreference time CT with the gate clock actual time RT. When the gateclock reference time CT and the gate clock actual time RT are the sameas each other, the gate clock signal may be the normal signal. When thegate clock reference time CT and the gate clock actual time RT aredifferent from each other, the gate clock signal may be the abnormalsignal. If the abnormal gate clock signal is input to the gate driver, adisplay panel may display an abnormal image. In an embodiment, thecomparator 620 may generate the clock recovery signal RS when the gateclock reference time CT and the gate clock actual time RT are differentfrom each other. The comparator 620 may transmit the clock recoverysignal RS to a gate controller 630. The clock recovery signal RS mayallow the gate controller 630 to change a count value of an abnormalon-clock signal ON CLK or a count value of an abnormal off-clock signalOFF CLK.

In an embodiment, the power supply voltage generator 600 may count theactivation period of the on-clock signal ON CLK or the off-clock signalOFF CLK. In one embodiment, for example, the power supply voltagegenerator 600 may further include a counter configured to count theactivation period of the on-clock signal ON CLK or the off-clock signalOFF CLK. The counter may be disposed inside the power supply voltagegenerator 600, or may be disposed outside the power supply voltagegenerator 600 to communicate with the power supply voltage generator600. As shown in FIG. 3, when the gate clock signal includes two phasesand four clocks, the counter may perform an operation of dividing theactivation period of the on-clock signal ON CLK or the off-clock signalOFF CLK into 1, 2, 3, and 4, and repeatedly counting the dividedactivation period. The gate clock signal may be controlled insynchronization with the count values of the on-clock signal ON CLK andthe off-clock signal OFF CLK. In one embodiment, for example, the gateclock signal may be synchronized with a corresponding count value of theon-clock signal ON CLK to rise from the gate low voltage to the gatehigh voltage. In one embodiment, for example, the gate clock signal maybe synchronized with a corresponding count value of the off-clock signalOFF CLK to fall from the gate high voltage to the gate low voltage.

In an embodiment, the display device may correct the gate clock signalinto the normal signal by increasing or decreasing the count value ofthe on-clock signal ON CLK or the off-clock signal OFF CLK when the gateclock reference time CT and the gate clock actual time RT are differentfrom each other (S260). In detail, the gate controller 630 may receivethe on-clock signal ON CLK and the off-clock signal OFF CLK from thedriving controller 200. The gate controller 630 may generate the gateclock signal based on the on-clock signal ON CLK and the off-clocksignal OFF CLK. The gate controller 630 may output the gate clock signalto the output terminal OP of the power supply voltage generator 600. Thegate controller 630 may feedback and input the gate clock signal to thecomparator 620. When the gate clock signal is the abnormal signal, thegate controller 630 may receive the clock recovery signal RS from thecomparator 620. The gate controller 630 may correct the gate clocksignal into a normal signal by increasing or decreasing the count valueof the on-clock signal ON CLK or the off-clock signal OFF CLK accordingto the clock recovery signal RS. In one embodiment, for example, thegate controller 630 may recover a count value before a loss of theon-clock signal ON CLK by decreasing the count value of the on-clocksignal ON CLK when the gate clock signal is the abnormal signal due tothe loss of the on-clock signal ON CLK. In addition, the gate controller630 may recover a count value before a loss of the off-clock signal OFFCLK by increasing the count value of the off-clock signal OFF CLK whenthe gate clock signal is the abnormal signal due to the loss of theoff-clock signal OFF CLK. As shown in FIG. 7, when a first off-clocksignal OFF CLK is lost, the gate controller 630 may increase a countvalue of a second off-clock signal OFF CLK from 1 to 2 based on theclock recovery signal RS. Similarly, the gate controller 630 mayincrease a count value of a third off-clock signal OFF CLK from 2 to 3.In this case, a first gate clock signal may be abnormally output,whereas a second gate clock signal, a third gate clock signal, and afourth gate clock signal may be synchronized with a normal off-clocksignal OFF CLK so as to be output as normal signals. Accordingly, asshown in FIG. 8, an image displayed on the display panel may be a normalimage except for data corresponding to the first gate clock signal,which is an abnormal signal. In other words, noise in a unit of line maybe generated in the display panel. Such noise in the unit of line maynot be generally recognized by a user, so that display quality defectsmay be minimized. Accordingly, according to the display device, visualrecognition of the noise by the user may be minimized, and the displayquality defects of the display device may be reduced.

FIG. 11 is a timing diagram showing another example of input and outputsignals of the power supply voltage generator 600 in FIG. 1.

Referring to FIGS. 1 and 11, FIG. 11 may show one embodiment of inputand output signals of the power supply voltage generator 600 when thegate clock signal includes four phases (e.g., 1 to 4 in the on-clocksignal ON CLK and the off-clock signal OFF CLK) and eight clocks (e.g.,first to eighth clock signals CKV1 to CKV8). The power supply voltagegenerator 600 may receive the on-clock signal ON CLK, the off-clocksignal OFF CLK, and the vertical start signal STV from the drivingcontroller 200. The power supply voltage generator 600 may generate thegate clock signal CKV and the gate start signal STVP based on theon-clock signal ON CLK, the off-clock signal OFF CLK, and the verticalstart signal STV. In such an embodiment, a rising time of each of gateclock signals at which the gate clock signal rises from a gate lowvoltage to a gate high voltage may be determined by a rising edge of theon-clock signal ON CLK. In such an embodiment, a falling time of each ofthe gate clock signals at which the gate clock signal falls from thegate high voltage to the gate low voltage may be determined by a fallingedge of the off-clock signal OFF CLK. Each of a plurality of gate clocksignals may have an activation period (e.g., a gate high voltage period)that partially overlaps an activation period of an adjacent gate clocksignal. The power supply voltage generator 600 may generate the gateclock signal CKV and the gate start signal STVP to output the generatedgate clock signal CKV and the generated gate start signal STVP to thegate driver 300. Although FIG. 11 shows an embodiment where the gateclock signals have four phases and eight clocks, embodiments of thedisclosure are not limited thereto, and the types of the gate clocksignal of the disclosure may include various phases and clocks, such as6 phases and 12 clocks, or 8 phases and 16 clocks.

The on-clock signal ON CLK and the off-clock signal OFF CLK may beabnormally output due to the malfunction of the driving controller 200caused by the external factor such as static electricity or a momentaryelectrical surge. In this case, the gate clock signal generated by thepower supply voltage generator 600 may also be an abnormal signal. Ifsuch an abnormal gate clock signal is input to the gate driver, thedisplay panel may display an abnormal image. In embodiments of thedisclosure, the display device may include: a display panel including agate line, a data line, and a pixel electrically connected to the gateline and the data line, where the display panel displays an image basedon input image data; a gate driver which outputs a gate signal to thegate line; a data driver which outputs a data voltage to the data line;and a power supply voltage generator 600 which provides a drivingvoltage to the display panel, the gate driver, and the data driver. Insuch embodiments, the power supply voltage generator 600 may generatethe gate clock signal based on the on-clock signal ON CLK and theoff-clock signal OFF CLK, and change the count value of the on-clocksignal ON CLK or the off-clock signal OFF CLK when the gate clock signalis the abnormal signal. Accordingly, in embodiments of the displaydevice of the disclosure, the visual recognition of the noise by theuser may be minimized, and the display quality defects of the displaydevice may be reduced.

According to embodiments of the display device and the method of drivingthe display device of the disclosure as described above, safety andreliability of the display device may be improved.

The invention should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete and will fully conveythe concept of the invention to those skilled in the art.

While the invention has been particularly shown and described withreference to embodiments thereof, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made therein without departing from the spirit or scope of theinvention as defined by the following claims.

What is claimed is:
 1. A display device comprising: a display panelincluding a gate line, a data line, and a pixel electrically connectedto the gate line and the data line, wherein the display panel displaysan image based on input image data; a gate driver which outputs a gatesignal to the gate line; a data driver which outputs a data voltage tothe data line; and a power supply voltage generator which provides adriving voltage to the display panel, the gate driver and the datadriver, wherein the power supply voltage generator generates a gateclock signal based on an on-clock signal and an off-clock signal andchanges a count value of the on-clock signal or the off-clock signalwhen the gate clock signal is an abnormal signal.
 2. The display deviceof claim 1, wherein the power supply voltage generator determineswhether the gate clock signal is the abnormal signal based on a lengthof an activation period of the gate clock signal.
 3. The display deviceof claim 2, wherein the power supply voltage generator calculates a gateclock reference time by calculating a time during which the activationperiod of the gate clock signal is maintained based on the on-clocksignal and the off-clock signal.
 4. The display device of claim 3,wherein the power supply voltage generator obtains a gate clock actualtime by feeding back the gate clock signal output from an outputterminal of the power supply voltage generator and determines the gateclock signal as the abnormal signal when the gate clock reference timeand the gate clock actual time are different from each other.
 5. Thedisplay device of claim 2, wherein the power supply voltage generatorcounts an activation period of the on-clock signal or the off-clocksignal and generates the gate clock signal corresponding to the countvalue of the on-clock signal or the off-clock signal.
 6. The displaydevice of claim 5, wherein the power supply voltage generator adjuststhe length of the activation period of the gate clock signal byincreasing or decreasing the count value of the on-clock signal or theoff-clock signal when the gate clock signal is the abnormal signal. 7.The display device of claim 2, wherein the power supply voltagegenerator includes: a calculator which calculates a gate clock referencetime by calculating a time during which the activation period of thegate clock signal is maintained based on the on-clock signal and theoff-clock signal; a comparator which obtains a gate clock actual time byfeeding back the gate clock signal output from an output terminal andcompares the gate clock reference time with the gate clock actual time;and a gate controller which outputs the gate clock signal to the outputterminal and corrects the gate clock signal into a normal signal byincreasing or decreasing the count value of the on-clock signal or theoff-clock signal when the gate clock signal is the abnormal signal. 8.The display device of claim 7, wherein the calculator calculates thegate clock reference time as a multiplication of a time during which anactivation period of the on-clock signal is maintained and a number oftypes of the gate clock signal.
 9. The display device of claim 7,wherein the comparator generates a clock recovery signal when the gateclock reference time and the gate clock actual time are different fromeach other and transmits the clock recovery signal to the gatecontroller.
 10. The display device of claim 7, wherein the gatecontroller recovers a count value before a loss of the on-clock signalby decreasing the count value of the on-clock signal when the gate clocksignal is the abnormal signal due to the loss of the on-clock signal.11. The display device of claim 7, wherein the gate controller recoversa count value before a loss of the off-clock signal by increasing thecount value of the off-clock signal when the gate clock signal is theabnormal signal due to the loss of the off-clock signal.
 12. A method ofdriving a display device, the method comprising: generating an on-clocksignal and an off-clock signal; generating a gate clock signal based onthe on-clock signal and the off-clock signal; determining whether thegate clock signal is an abnormal signal based on a length of anactivation period of the gate clock signal; and changing a count valueof the on-clock signal or the off-clock signal when the gate clocksignal is the abnormal signal.
 13. The method of claim 12, furthercomprising: calculating a gate clock reference time by calculating atime during which the activation period of the gate clock signal ismaintained based on the on-clock signal and the off-clock signal. 14.The method of claim 13, wherein a gate clock actual time is obtained byfeeding back the gate clock signal output from an output terminal, andthe gate clock signal is determined as the abnormal signal when the gateclock reference time and the gate clock actual time are different fromeach other.
 15. The method of claim 12, further comprising: counting anactivation period of the on-clock signal or the off-clock signal; andgenerating the gate clock signal corresponding to the count value of theon-clock signal or the off-clock signal.
 16. The method of claim 15,wherein the length of the activation period of the gate clock signal isadjusted by increasing or decreasing the count value of the on-clocksignal or the off-clock signal when the gate clock signal is theabnormal signal.
 17. The method of claim 12, further comprising:calculating a gate clock reference time by calculating a time duringwhich the activation period of the gate clock signal is maintained basedon the on-clock signal and the off-clock signal; obtaining a gate clockactual time by feeding back the gate clock signal output from an outputterminal; and comparing the gate clock reference time with the gateclock actual time, wherein the gate clock signal is output to the outputterminal, and the gate clock signal is corrected into a normal signal byincreasing or decreasing the count value of the on-clock signal or theoff-clock signal when the gate clock signal is the abnormal signal. 18.The method of claim 17, wherein the calculating the gate clock referencetime includes: calculating the gate clock reference time as amultiplication of a time during which an activation period of theon-clock signal is maintained and a number of types of the gate clocksignal.
 19. The method of claim 17, wherein the comparing the gate clockreference time with the gate clock actual time includes: generating aclock recovery signal when the gate clock reference time and the gateclock actual time are different from each other.
 20. The method of claim17, wherein the on-clock signal is recovered to have a count valuebefore a loss of the on-clock signal by decreasing the count value ofthe on-clock signal when the gate clock signal is the abnormal signaldue to the loss of the on-clock signal, and the off-clock signal isrecovered to have a count value before a loss of the off-clock signal byincreasing the count value of the off-clock signal when the gate clocksignal is the abnormal signal due to the loss of the off-clock signal.